Kp Mosfet



Mosfet characteristics using pspice pspice tutorials how to use pspice on analog and digital circuits, learn pspice in simple way, simple practicals in pspic. MOSFET (M1) and then, on the edit menu, select “Edit PSpice Model”. What we want to put into the model are values of K n and V TN appropriate to the 2N7000. The edit box is shown, as modified, as Figure 3. You need to know what to call the parameters you want to change.

A P-Channel MOSFET is a type of MOSFET in which the channel of the MOSFET is composed of a majority of holes as current carriers. When the MOSFET is activated and is on, the majority of the current flowing are holes moving through the channels.

This is in contrast to the other type of MOSFET, which are N-Channel MOSFETs, in which the majority ofcurrent carriers are electrons.

Before, we go over the construction of P-Channel MOSFETs, we must go over the 2 types that exist. There are 2 types of P-Channel MOSFETs, enhancement-type MOSFETs and depletion-type MOSFETs.

A depletion-type MOSFET is normally on (maximum current flows from source to drain) when no differencein voltage exists between the gate and source terminals. However, if a voltage is applied to its gate lead, the drain-source channel becomes more resistive, until the gate voltage is so high, the transistor completely shuts off. An enhancement-type MOSFET is the opposite. It is normally off when the gate-source voltage is 0V(VGS=0). However, if a voltage is applied to its gate lead, the drain-source channel becomesless resistive.

In this article, we will go over how both P-Channel enhancement-type and depletion-type MOSFETs are constructed and operate.

How P-Channel MOSFETs Are Constructed Internally


An P-Channel MOSFET is made up of a P channel, which is a channel composed of a majority of hole current carriers. The gate terminals are made up of N-type material.

Depending on the voltage quantity and type (negative or positive)determines how the transistor operates and whether it turns on or off.


How a P-Channel Enhancement-type MOSFET Works


How to Turn on a P-Channel Enhancement Type MOSFET

To turn on a P-Channel Enhancement-type MOSFET, apply a positive voltage VS to the source of the MOSFET and apply a negative voltage to the gate terminal of the MOSFET (the gate must be sufficiently more negative than the threshold voltage across the drain-source region(VG

So with a sufficient positive voltage, VS, to the source and load, and sufficient negative voltage applied to the gate, the P-Channel Enhancement-type MOSFET is fully functional and is in the active 'ON' mode of operation.

How to Turn Off a P-Channel Enhancement Type MOSFET

Spice Mosfet Kp

To turn off a P-channel enhancement type MOSFET, there are 2 steps you can take. You can either cut off the bias positive voltage, VS, that powers the source. Or you can turn off the negative voltagegoing to the gate of the transistor.

How a P-Channel Depletion-type MOSFET Works

How to Turn on a P-Channel Depletion Type MOSFET

To turn on a P-Channel Depletion-Type MOSFET, for maximum operation, the gate voltage feeding the gate terminal should be 0V. With the gate voltage being 0V, the drain current is at is largest value and the transistor is in the active 'ON'region of conduction.

So, again, to turn on a P channel depletion-type MOSFET, positive voltage is applied to the source of the p-channel MOSFET. So we power the source terminal of the MOSFET with VS, a positive voltage supply. With a sufficient positive voltage, VS, and no voltage (0V) applied to the base, the P-channel Depletion-type MOSFET is in maximum operation and has the largest current.

How to Turn Off a P-Channel Depletion Type MOSFET

To turn off a P-channel MOSFET, there are 2 steps you can take. You can either cut off the bias positivevoltage, VDD, that powers the drain. Or you can apply a negative voltage to the gate. When a negativevoltage is applied to the gate, the current is reduced. As the gate voltage, VG, becomes more negative, the current lessens until cutoff, which is when then MOSFET is in the 'OFF' condition. This stops a large source-drain current.

So ,again, as negative voltage is applied to the gate terminal of the P channel depletion-type MOSFET, the MOSFET conducts less and less current across the source-drain terminal. When the gate voltage reaches a certain negative voltage threshold, it shuts the transistor off. Negative voltage shuts the transistor off. This is for a depletion-type P-channel MOSFET.

Ltspice nmos model

MOSFET transistors are used for both switching and amplifying applications. MOSFETs are perhaps the most popular transistors used today. Their high input impedance makes them draw very little input current, they are easy to make, can be made very small, and consume very little power.

Related Resources

How to Build a P-Channel MOSFET Switch Circuit
N-Channel MOSFET Basics
N Channel JFET Basics
P Channel JFET Basics
Types of Transistors


Manuals >Nonlinear Device Models Volume 1 >UCB MOS Level 2 and 3 Characterization
Print version of this Book (PDF file)

MOSFET Model Parameters

The following table lists parameters for the three model levels according to DC and cv extraction in IC-CAP. (Some of these parameters are redundant and therefore only a subset of them is extracted in IC-CAP.) Table 76 describes model parameters by related categories and provide default values. The parameter values are displayed in the Circuit folder. Table 77 lists setup attributes.

Table 75 Summary of UCB MOSFET Controlling Model Parameters

LEVEL 1

LEVEL 3

Classical
VTO, GAMMA, PHI KP IS, JS, TOX
NSUB, UO, UCRIT, UEXP, UTRA, NFS, NSS, TPG
NSUB, UO, THETA, NFS, NSS, TPG
Short-channel


LD, XJ
LD, XJ
Narrow-width




DELTA, WD†††
Saturation
LAMBDA
NEFF, VMAX
ETA, KAPPA
External resistance
NRD††, NRS†† RD, RS




Junction capacitance
AD††, AS††, CBD, CBS CJ, FC, MJ, PB




Sidewall capacitance
PD††, PS††, CSJW, MJSW




Overlap capacitance
CGBO, CGDO, CGSO




General
LEVEL, L††, W††




IC-CAP Temperature Specification
TNOM (system variable)




Notes:
LEVEL 2 and LEVEL 3 also include LEVEL 1 parameters.
†† Indicates device parameters (model and device parameters are listed together).
††† WD does not exist in the SPICE UCB version; it has been added to some SPICE versions and is included in IC-CAP. If WD is not in your simulator, ignore the result (set to zero), or subtract 2·WD from the channel width. In the MOS model files provided with IC-CAP, the width specification W in each of the DUTs has been modified to subtract the value of 2·WD from the drawn width. WD is specified in Model Variables.

Table 76 UCB MOSFET Parameters
Description
Capacitance
CGBO
Gate to Bulk Overlap Capacitance. Capacitance due to design rules that require the gate be extended beyond the channel by some amount. Not voltage dependent. Total Cgb capacitance equals Cgbo times channel length.
0 F/m
CGDO
Gate to Drain Overlap Capacitance. Capacitance due to the lateral diffusion of the drain in an Si gate MOSFET. Not voltage dependent. Total Gcd capacitance equals Cgdo times the channel width.
0 F/m
CGSO
Gate to Source Overlap Capacitance. Capacitance due to the lateral diffusion of the source in an Si gate MOSFET. Not voltage dependent because it is not a junction capacitance. Total Cgs capacitance equals Cgso times channel width.
0 F/m
CJSW
Zero Bias Junction Sidewall Capacitance. Models the nonlinear junction capacitance between the drain and the source junction sidewall. (Pd + Ps) * CJSW = total junction sidewall capacitance.
0 F/m
MJSW
Grading Coefficient of Junction Sidewall. Models the grading coefficient for the junction sidewall capacitance.
0.33
PB
Bulk Junction Potential. Models the built-in potential of the bulk-drain or bulk-source junctions. The default is usually adequate.
0.8 volt
FC
Forward Bias Non-Ideal Junction Capacitance Coefficient. Models the point (FC * PB) at which junction capacitance makes the transition between forward and reverse bias.
0.5
Electrical Process
IS
Substrate Junction Saturation Current. Helps model current flow through the bulk-source or bulk-drain junction.
1×10-16 Amp
JS
Substrate Junction Saturation Current/m2. Js equals Is divided by the junction area. For example, Isd=Js*Ad where Ad is the drain area.
1×10-4 A/m2
RD
Drain Ohmic Resistance. This parameter is geometry independent in SPICE and IC-CAP. In fact, it is inversely proportional to channel width.
0 Ohm
UCRIT
Critical Field for Mobility Degradation. Used in level=2 model only.
1000 V · cm-1
UEXP
Critical Field Exponent. Used in level=2 model only.
0
UO
Surface Mobility at Low Gate Levels. Specifies mobility in level=2 and level=3 models. In the level=2 model, if Kp is UTRA
600 cm2/(V · S)
UTRA
Transverse Field Coefficient. Used in level=2 model only. Set UTRA to 0 to obtain same result as SPICE.
0
VMAX
Maximum Drift Velocity of Carriers. Determines whether Vdsat is a function of scattering velocity limited carriers or a function of drain depletion region pinch-off.VMAX is valid only for level=2 and level=3 models. If VMAX is specified, the scattering velocity limited carrier model is used to determine Vdsat.
0 m · s-1
NEFF
Total Channel Charge. A multiplicative factor of NSUB, NEFF determines saturated output conductance. Used only in the level=2 model, and only when Vmax is specified.
1.0
Physical Process
LD
Lateral Diffusion Coefficient. Used to determine the effective channel length.
0 Meter
TOX
Oxide Thickness. Used when calculating conduction factor, backgate bias effects, and gate-channel capacitances.
100×10-9 Meter
TPG
Type of Gate. Indicates whether gate is of metal or poly-silicon material (0=aluminum; 1=opposite substrate; -1=same as substrate). Used in calculating threshold voltage when Vto is not specified.
1
WD
Channel Width Reduction. Used to determine the effective channel width This parameter is assumed to be 0 in SPICE.
0 Meter
XJ
Metallurgical Junction Depth. Defines the distance into the diffused region around the drain or source at which the dopant concentration becomes negligible. Used to model some short channel effects.
0 Meter
Threshold Related
NFS
Effective Fast Surface State Density. Used to determine subthreshold current flow. Not valid for extracting simple linear region classical parameters.
0 cm-2
NSS
Effective Surface Charge Density. Used to calculate threshold voltage when Vto is not specified.
0 cm-2
NSUB
Substrate Doping Concentration. Used in most calculations for electrical parameters. It is more accurate to specify Vto rather than deriving it from NSUB. However, NSUB should be specified when modeling the back gate bias dependency of Vto.
1 × 1015 cm-3
DELTA
Width Effect on Threshold Voltage. Used in LEVEL=2 and LEVEL=3 models to shift threshold voltage for different channel widths.
0
ETA
Static Feedback. Used in LEVEL=3 model to decrease threshold for higher drain voltage.
0
GAMMA
Bulk Threshold. The proportionality factor that defines the threshold voltage to backgate bias relationship. Used in the derivation of Vto, Ids, and Vdsat. If not specified in LEVEL=2 and LEVEL=3 models, it is computed from NSUB.
0 V1/2
VTO
Extrapolated Zero Bias. Threshold Voltage Models the onset of strong inversion in the LEVEL=1 model. Marks the point at which the device starts conducting if weak inversion current is ignored.
0 Volt
Electrical
KAPPA
Saturation Field Factor. Used in the level=3 model to control saturation output conductance.
0.2
KP
Intrinsic Transconductance. If not specified for the level=2 model, KP is computed from Kp=u0*Cox. In some of the literature, KP may be shown as k'. The default for the LEVEL=1 model is 2x10e-5.
0 A/V2
LAMBDA
Channel Length Modulation Models. The finite output conductance of a MOSFET in saturation. It is equivalent to the inverse of Early Voltage in a bipolar transistor. Specifying this parameter ensures that a MOSFET will have a finite output conductance when saturated. In the level=1 model, if lambda is not specified a zero output conductance is assumed. In the level=2 model, if lambda is not specified, it will be computed.
0 V-1
PHI
Surface Potential Models. The surface potential at strong inversion.If not specified in level=2 and level=3 models, it is computed as PHI=2kT/q *ln(Nsub/ni). PHI also may be shown as 2*PHIb.
0 Volt
THETA
Mobility Reduction. Used in level=3 to model the degradation of mobility due to the normal field.
0 V-1
Device Geometry
L
Drawn or Mask Channel Length. Physical length of the channel.
1×10-4 Meter
W
Drawn or Mask Channel Width. Physical width of channel.
1×10-4 Meter
AD
Area of Drain Area of drain diffusion. Used in computing Is (from Js), and drain and source capacitance from Cbd=CjAd.
0 m2
AS
Area of Source diffusion. Can be used as described for AD.
0 m2
NRD
Equivalent Squares in Drain Diffusion. Number of equivalent squares in the drain diffusion. Multiplied by Rsh to obtain parasitic drain resistance (Rd).
1.0
NRS
Equivalent Squares in Source Diffusion. Number of equivalent squares in the source diffusion. Multiplied by Rsh to obtain parasitic source resistance (Rs).
1.0
PD
Drain Junction Perimeter. Used with CJSW and MJSW to model the junction sidewall capacitance of the drain.
0 Meter
PS
Source Junction Perimeter. Used with CJSW and MJSW to model the junction sidewall capacitance of the source.
0 Meter
General
LEVEL
Extraction Level. Specifies one of four extraction levels.
1

Table 77 MOSFET Setup Attributes
DUT/
Setup

Outputs
Function
LEVEL 2 Model
large/
idvg

vg, vb, vd, vs
id
extract
MOSDC_lev2_lin_large
NSUB, UO, UEXP, VTO
optimize
NSUB, UO, UEXP, VTO
narrow/
idvg

//
//
extract
MOSDC_lev2_lin_narrow
DELTA, WD
optimize
DELTA, WD
short/
idvg

//
//
extract
MOSDC_lev2_lin_short
LD, XJ
optimize
LD, RD, RS, XJ
short/
idvd

vd, vg, vb, vs
id
extract
MOSDC_lev2_sat_short
NEFF, VMAX
optimize
NEFF, VMAX
cbd1/
cjdarea

vb, vd
cbd
set_CJ extract
Program
initial zero bias CJ
Optimize
CJ, MJ, PB
cbd2/
cjdp3erimeter

vb, vd
cbd
extract
MOSCV_total_cap
CJ, MJ, CJSW, MJSW, PB
LEVEL 3 Model
large/
idvg

vg, vb, vd, vs
id
extract
MOSDC_lev3_lin_large
NSUB, UO, THETA, VTO
optimize
NSUB, UO, THETA, VTO
narrow/
idvg

//
//
extract
MOSDC_lev3_lin_narrow
DELTA, WD
optimize
DELTA, WD
short/
idvg

//
//
extract
MOSDC_lev3_lin_short
LD, RD, RS, XJ
optimize
LD, RD, RS, XJ
short/
idvd

vd, vg, vb, vs
id
extract
MOSDC_lev3_sat_short
ETA, KAPPA
optimize
ETA, KAPPA
cbd1/
cjdarea

vb, vd
cbd
set_CJ
extract

Program
initial zero bias CJ
Optimize
CJ, MJ, PB
cbd2/
cjdperimeter

vb, vd
cbd
extract
MOSCV_total_cap
CJ, MJ, CJSW, MJSW, PB

Ltspice Mosfet Kp